Haswell (microarchitecture)
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Haswell is the codename for a processor microarchitecture to be developed by Intel as the successor to Sandy Bridge. Haswell uses the 22 nm process (the tock after Ivy Bridge) and will implement fused multiply-add (FMA3) instructions.[1] Like Nehalem, Haswell is to be developed by Intel's Oregon team.[2] CPUs based on the Haswell microarchitecture are expected to be released as soon as early 2013.[3] There are currently no details regarding this microarchitecture's development.
[edit] Architecture
- 22 nm process.
Haswell is expected to have the following features:[1][4]
- Up to 8 cores available.
- An entirely new cache design.
- 3D tri-gate transistors.
- New advanced power saving mechanisms.
- Possible on-package vector coprocessor.
- Fused multiply-add (FMA3) instructions.
- 64kB data + 64kB instruction L1 cache per core, 4-way associativity.
- 1MB L2 cache per core, 4-way associativity.
- Up to 16MB L3 cache shared by all cores, 8-way associativity.
[edit] Broadwell
In keeping with Intel's tick-tock principle, the 14 nm[5] shrink of Haswell is due out approximately one year after the introduction of the microarchitecture and will be codenamed Broadwell.[6]
[edit] References
- ^ a b Doc, TB. "IDF Shanghaï : From Nehalem to Haswell". CanardPC (French). http://www.canardplus.com/dossier-35-200-Processeur_de_Nehalem_a_Haswell.html. Google translate
- ^ Intel Developer Forum – Technology Insight
- ^ http://translate.google.com/translate?hl=en&sl=ja&u=http://pc.watch.impress.co.jp/&ei=XpXUS--yEsWqlAe30oHtDA&sa=X&oi=translate&ct=result&resnum=2&ved=0CCQQ7gEwAQ&prev=/search%3Fq%3Dpc%2Bwatch%26hl%3Den%26safe%3Doff
- ^ http://translate.google.com/translate?hl=en&sl=ja&u=http://pc.watch.impress.co.jp/docs/2008/0818/kaigai459.htm&sa=X&oi=translate&resnum=4&ct=result&prev=/search%3Fq%3Dsandy%2Bbridge%2Bsite:pc.watch.impress.co.jp%26hl%3Den
- ^ Intel Presentation: 22nm Details
- ^ After Intel's Haswell comes Broadwell - SemiAccurate
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